1. Field of the Invention
The present invention generally relates to the fabrication of semiconductor devices and specifically to a transistor device with a gradient doped source/drain and a method for forming the transistor device.
2. Description of the Prior Art
Integration of the integrated circuit semiconductor device has gradually increased. The size of the semiconductor device is shorter and shorter as well. Therefore, it is important to maintain good operative condition even though the size of the semiconductor is measured in amounts as small as angstroms. This is particularly true in the case of the conventional C.M.O.S. device, which is usually used as a high-voltage device. Generally the conventional horizontal-direction C.M.O.S. structure will occupy much space of the chip due. Also, the channel and drift area of the conventional C.M.O.S. will occupy the horizontal-direction space of chip. Therefore, if possible, it is necessary to modify the geometry of C.M.O.S. device.
One approach to minimize the degradation is to reduce the electric field at the drain region from achieving sufficient energy to be injected into the gate oxide. This is achieved by grading the junction of the drain by doing two implants and is designed to create a lighter doped region beyond the normal N+ drain region. Also, this can be done by offsetting the heavier implant with a sidewall spacer foxing the drain structure, sometimes which is called a lightly doped drain (LDD).
Another approach is simply to do two implants of phosphorus and arsenic in the same region to form a structure which is sometimes called a double doped (or double diffused) drain (DDD). The electric field in the drain region is reduced for both these structures due to the graded drain doping.
In accordance with the present invention, a method is provided for forming Complementary Metal-Oxide Semiconductor that is substantially achieved. In one embodiment, an improved C.M.O.S. fabrication process which uses separate masking steps to pattern N-channel and P-channel transistor gates from a single layer of conductivity-doped polycrystalline silicon (polysilicon) and multi gradientially conductivity-doped.
The present invention provides a method for forming a transistor with a gradient doped source/drain. The method comprises the following steps. First, two N-wells are formed in a substrate and first N-wells are separated in both sides of the substrate. Then, two second N-wells are formed in the substrate and second N-wells overlie first N-wells. An implanting concentration of first N-wells is smaller than an implanting concentration of second N-wells. Next, a field oxide region is formed in the substrate between first N-wells and the field oxide region overlies a portion of second N-wells. Thereafter, a portion of the field oxide region and the substrate are removed to form a trench in the substrate, wherein the remaining field oxide region overlies the second N-wells. Next, a gate oxide layer is formed on a bottom surface and a sidewall of the trench. Then, a polysilicon gate is formed on the substrate. The trench is filled with the polysilicon gate and the polysilicon gate overlies a portion of the remaining field oxide region. Last, a N+-type source/drain is formed in the substrate and the N+-type source/drain is adjacent to the remained field oxide region and overlies the second N-wells.